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www.gennum.com gs1535 hd-linx ii? multi-rate sdi automatic reclocker gs1535 data sheet 18557 - 8 february 2005 1 of 22 key features ? smpte 292m, 259m and 344m compliant ? supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 mb/s ? supports dvb-asi at 270mb/s ? auto and manual modes for rate selection ? standards indication in auto mode ? 4:1 input multiplexor ? lock detect output ? on-chip input and output termination ? differential inputs and outputs ? configuarble automatic mute or bypass when not locked ? manual bypass function ? sd/hd indication output to control gs1528 dual slew-rate cable driver ? pb-free and green ? single 3.3v power supply ? operating temperature range: 0c to 70c applications ? smpte 292m, smpte 259m and smpte 344m serial digital interfaces description the gs1535 multi-rate seri al digital reclocker is designed to automatically recover the embedded clock signal and re-time the data from a smpte 292m, smpte 259m or smpte 344m compliant digital video signal. the device removes the high frequency jitter components from the bit-serial stream. input termination is on-chip for seamless matching to 50 ? transmission lin es. an lvpecl co mpliant output interfaces seamlessly to the gs1528 cable driver the gs1535 can operate in either auto or manual rate selection mode. in auto mode the gs1535 automatically detects and locks onto an incoming smpte sdi data signal from 143 mb/s to 1.485 gb/s. for single rate data systems, the gs1535 can be configured to operate in manual mode. in both modes, the gs1535 requires only one external crystal to set the vco frequency when not locked and provides adjustment free operation. in systems which require passing non-smpte data rates, the gs1535 will automatically or manually enter a bypass mode in order to pass the signal without reclocking. the asi/177 input pin allows for manual selection of support of either 177mb/s or dvb-asi inputs. gs1535 functional block diagram xtal+ xtal- xtal out- xtal out+ ddi_sel[1:0] ddi 1 ddi 2 ddi 3 ddi 0 lf+ lf- kbb ddo_mute ddo/ddo autobypass bypass ld auto/man ss[2:0] asi/177 xtal osc buffer data buffer vco bypass logic divide by 2,4,6,8,12,16 phase frequency detector divide by 152, 160, 208 control logic charge pump m u x d a t a m u x m u x re-timer phase detector
gs1535 data sheet 18557 - 8 february 2005 2 of 22 contents key features.................................................................................................................1 applications................................................................................................................... 1 description .................................................................................................................... 1 1. pin out ..................................................................................................................... .3 1.1 pin assignment ...............................................................................................3 1.2 pin descriptions ..............................................................................................4 2. electrical characteristics ...........................................................................................7 2.1 absolute maximum ratings ............................................................................7 2.2 dc electrical characteristics ............... ...........................................................7 2.3 ac electrical characteristics .............. .............................................................8 2.4 input/output circuits .....................................................................................10 3. detailed description .................................. ..............................................................13 3.1 slew rate phase lock loop (s-pll) .. .........................................................13 3.2 vco ..............................................................................................................14 3.3 charge pump ................................................................................................14 3.4 frequency acquisition loop ?the phas e-frequency detector .......... .........14 3.5 phase acquisition loop ? the phase detector ...........................................15 3.6 4:1 input mux ................................................................................................15 3.7 automatic and manual data rate select ion ............ .............. .............. .........16 3.8 bypass mode ................................................................................................17 3.9 dvb/asi operation .......................................................................................17 3.10 lock ..........................................................................................................17 3.11 output drivers .............................................................................................18 3.12 output mute ................................................................................................18 4. application reference design .................................................................................19 4.1 typical application circuit .............................................................................19 5. references..............................................................................................................20 6. package & ordering information .............................................................................20 6.1 package dimensions ....................................................................................20 6.2 packaging data .............................................................................................21 6.3 ordering information .....................................................................................21 7. revision history ......................................................................................................22
gs1535 data sheet 18557 - 8 february 2005 3 of 22 1. pin out 1.1 pin assignment p xtal_out- xtal_out+ gnd vee_ddo vcc_ddo ddo ddo_vtt gnd vcc_int vee_int rsvd rsvd gnd gnd kbb ddi_sel0 ddi_sel1 bypass autobypass vcc_vco vee_vco ss0 ss1 ss2 ld rsvd vcc_dig vee_dig gnd ddi0 ddi0_vtt gnd ddi1_vtt gnd ddi1 ddi2_vtt gnd ddi2 ddi3_vtt gnd ddi3 gnd lf- lf+ vcc_cp vee_cp rsvd rsvd vcc rsvd vcc gnd xtal- xtal+ gs1535 64 pin lqfp top view ddi3 ddi2 ddi1 ddi0 auto/man sd/hd ddo_mute rsvd ddo asi/177 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
gs1535 data sheet 18557 - 8 february 2005 4 of 22 1.2 pin descriptions table 1-1: pin descriptions pin number name type description 1, 3 ddi0, ddi0 input serial digital differential input 0. 2 ddi0_vtt passive center tap of two 50 ? on-chip termination resistors between ddi0 and ddi0 . 5, 7 ddi1,ddi1 input serial digital differential input 1. 6 ddi1_vtt passive center tap of two 50 ? on-chip termination resistors between ddi1 and ddi1 . 9, 11 ddi2, ddi2 input serial digital differential input 2. 10 ddi2_vtt passive center tap of two 50 ? on-chip termination resistors between ddi2 and ddi2 . 13, 15 ddi3, ddi3 input serial digital differential input 3 . 14 ddi3_vtt passive center tap of two 50 ? on-chip termination resistors between ddi3 and ddi3 . 17, 18 ddi_sel[1:0] logic input serial digital input select. 19 bypass logic input bypasses the reclocker stage (active high). when bypass is high, it overwrites the autobypass setting. 20 autobypass logic input automatically bypasses the reclocker stage when the pll is not locked (active high). 21 auto/man logic input when active, the standard is automatically detected from the input data rate. ddi_sel1 ddi_sel0 input selected 00 ddi0 01 ddi1 10 ddi2 11 ddi3
gs1535 data sheet 18557 - 8 february 2005 5 of 22 24, 25, 26 ss[2:0] bidirectional when auto/man is high, ss[0:2] are outputs, displaying the data rate to which the pll has locked. when auto/man is low, ss[0:2] are inputs, forc ing the pll to lock only to a selected data rate. 27 asi/177 logic input disables 177mbps data rate in t he auto data rate detection circuit. this prevents a false lock to 177mbps when using dvb/asi. 28 ld output lock detect. high when the pll is locked. 29 rsvd reserved do not connect. 33 sd/hd output this signal is low when the reclocker has locked to 1.485gbps or 1.485/1.001gbps, and high when the reclocker has locked to 143mbps, 177mbps, 270mbps, 360mbps, or 540mbps. 34 kbb analog input controls the loop bandwidth of t he pll. leave this pin floating for serial reclocking ap plications. 36 ddo_mute logic input mutes the ddo/ddo outputs, when not in bypass mode. 44, 46 ddo , ddo output differential serial digital outputs. 45 ddo_vtt passive center tap of two 50 ? on-chip termination resistors between ddo and ddo .. 50, 51 xtal_out+, xtal_out- output differential buffered outputs of the reference oscillator. 52, 53 xtal+, xtal- input reference crystal input. connect to the go1535. 62, 63 lf+, lf- passive loop filter capacitor connection. (c lf = 47nf). 4, 8, 12,16, 32, 35, 37, 43, 49, 54, 64 gnd passive recommended connect to gnd. 43 gnd_drv passive recommended connect to gnd. table 1-1: pin descriptions (continued) pin number name type description ss2 ss1 ss0 data rate selected/forced (mb/s) 0 0 0 143 0 0 1 177 0 1 0 270 0 1 1 360 1 0 0 540 1 0 1 1483.5/1485
gs1535 data sheet 18557 - 8 february 2005 6 of 22 55, 57 vcc passive recommend connect to 3.3v. 22 vcc_vco power most positive power supply connection for the internal vco section. connect to 3.3v. 30 vcc_dig power most positive power supply connection for the internal glue logic. connect to 3.3v. 41 vcc_int power most positive power supply connection. connect to 3.3v. 47 vcc_ddo power most positive power supply connection for the ddo/ddo output driver. connect to 3.3v. 61 vcc_cp power most positive power supply connection for the internal charge pump. connect to 3.3v. 23 vee_vco power most negative power supply c onnection for the internal vco section. connect to ground. 31 vee_dig power most negative power supply c onnection for the internal glue logic. connect to ground. 42 vee_int power most negative power supply connection. connect to ground. 48 vee_ddo power most negative power supply connection for the ddo/ddo output driver. connect to ground. 60 vee_cp power most negative power supply c onnection for the internal charge pump. connect to ground. 38, 39, 40, 56, 58, 59 rsvd reserved do not connect. table 1-1: pin descriptions (continued) pin number name type description
gs1535 data sheet 18557 - 8 february 2005 7 of 22 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage +3.6 v dc input esd voltage 500v storage temperature range -50c< t s < 125c inputs v cc + 0.5v table 2-2: dc electrical characteristics v cc = 3.3v, t a = 0c to 70c, unless otherwise shown parameter conditions symbol min typ max units test levels supply voltage operating range v cc 3.135 3.3 3.465 v 3 power consumption t a =25c 408 600 849 mw 5 supply current t a =25c i cc 130 182 245 ma 1 logic inputs ddi_sel[1:0], bypass, autobypass, auto/man , asi/177 , sdo_mute high v ih 2.0 - - v 3 low v il --0.8v3 logic outputs sd/hd and ld 250a load v oh 3.2 - - v 3 v ol --0.6v3 bi-directional pins ss[2:0], auto/man = 0 (manual mode) high v ih 2.0 - - v 3 low v il --0.8v3 bi-directional pins ss[2:0], auto/man = 1 (auto mode) high v oh 2.6 - v 1 low v ol --0.6v1
gs1535 data sheet 18557 - 8 february 2005 8 of 22 2.3 ac electrical characteristics xtal_out+, xtal_out- high v oh -v cc -v7 low v ol -v cc - 0.285 - v 7 serial input voltage common mode 1.65 + (v sid /2) -v cc - (v sid /2) v 1 output voltage sdo, sdo common mode -v cc - v od /2 - v 1 test levels 1. production test at room temperature and nominal suppl y voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply vo ltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/c haracterization data of similar product. 9. indirect test. table 2-2: dc electrical characteristics v cc = 3.3v, t a = 0c to 70c, unless otherwise shown parameter conditions symbol min typ max units test levels table 2-3: ac electrical characteristics v cc = 3.3v, t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test levels serial input data rate 143 - 1485 mb/s 3 serial input jitter tolerance worst case modulation eg. square wave modulation 143, 270, 360, 1485 mb/s 0.8 - - ui 1 pll lock time - asynchronous t alock - 5 10 ms 6,7 pll lock time - synchronous t slock c lf =47nf sd/hd =0 0.29 - - s6,7 sd/hd =1 0.16 - - s6,7 serial output rise/fall time (20% - 80%) t rsdo 50 ? load (on chip) - 114 - ps 6,7 t fsdo - 106 - ps serial input - signal swing v sid 50 ? load (on chip) 100 - 800 mv p-p 6,7 serial output - signal swing v od differential (across 100 ?). 1400 - 2000 mv p-p
gs1535 data sheet 18557 - 8 february 2005 9 of 22 serial output jitter (additive) t ij kbb=float, prn, 2 23 -1 143mb/s - 0.02 - ui 1 177mbs - 0.02 - ui 1 270mb/s - 0.02 0.09 ui 1 360mbs - 0.03 - ui 1 540mbs - 0.03 0.09 ui 1 1485mb/s - 0.06 0.13 ui 1 bypass - 0.06 0.13 ui 1 loop bandwidth bw loop 1.485 gb/s kbb = float -1.5-mhz6,7 1.485 gb/s kbb = gnd <0.1db peaking -3.5-mhz6,7 270 mb/s kbb = float - 520 - khz 6,7 270 mb/s kbb = gnd - 1000 - khz 6,7 test levels 1. production test at room temperature and nominal suppl y voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/c haracterization data of similar product. 9. indirect test. table 2-3: ac electrical characteristics v cc = 3.3v, t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test levels
gs1535 data sheet 18557 - 8 february 2005 10 of 22 2.4 input/output circuits figure 2-1: ttl inputs figure 2-2: crystal input figure 2-3: serial data outputs v ref 5k 10p 250r 250r 5k xtal+ xtal- 50 sdo sdo 50
gs1535 data sheet 18557 - 8 february 2005 11 of 22 figure 2-4: loop filter figure 2-5: crystal ouput buffer figure 2-6: kbb lf+ lf- 1k 1k xtal out- xtal out+ 500r v ref kbb
gs1535 data sheet 18557 - 8 february 2005 12 of 22 figure 2-7: indicator outputs: hd/sd , ld figure 2-8: serial data inputs figure 2-9: standard select/indication bi-directional pins 25k 50 ddi[3:0] ddi[3:0] 1k 1k 50 ddi_vtt v ref ss[2:0]
gs1535 data sheet 18557 - 8 february 2005 13 of 22 3. detailed description the gs1535 is a multi-standard retimer for se rial digital sdtv signals at 143, 177, 270, 360 and 540 mb/s, and hdtv signals at 1.485 gb/s and 1.485/1.001 gb/s. 3.1 slew rate phase lock loop (s-pll) the term ?slew? refers to the output phase of the pll in response to a step change at the input. linear plls have an output phase response characterized by an exponential response whereas an s-pll?s output is a ramp response (see figure 3-1 ). because of this non-linear respon se characteristic, traditional small signal analysis is not possible with an s-pll. figure 3-1: pll characteristics the s-pll offers several advantages over the linear pll. the loop bandwidth of an s-pll is independant of the transition density of the input data. pseudo-random data has a transition density of 0.5 ve rses a pathological signal which has a transition density of 0.05. the lo op bandwidth of a linear pll will change proportionally with this change in transition density. with an s-pll, the loop bandwidth is defined by the jitter at the data input. this translates to infinite loop bandwidth with a zero jitter input signal. this allows the loop to correct for small variations in the input jitter quickly, resulting in very lo w output jitter. the loop bandwidth of the gs1535?s pll is defined at 0.2ui of input jitter. the gs1535?s pll consists of two acquisi tion loops. first is the frequency acquisiton (fa) loop. this loop is active when the device is not locked and is used to achieve lock to the supported data rates. second is the phase acquisition (pa) loop. once locked, the pa loop tracks the incomming data and makes phased corrections to produce a re-clocked output. 0.2 0.1 0.0 input output slew pll response phase (ui) 0.2 0.1 0.0 input output linear (conventional) pll response phase (ui)
gs1535 data sheet 18557 - 8 february 2005 14 of 22 3.2 vco the internal vco of the gs1535 is a ring oscillator. it is trimmed at the time of manufacture to capture all sd and hd data rates over temperature, and operation voltage ranges. integrated into the vco is a series of programmable dividers, to achieve all serial data rates, as well as additional divi ders for the frequency acquisition loop. 3.3 charge pump a common charge pump is used for the gs1535?s pll. during frequency acquisition, the charge pump has two states, ?pump-up? and ?pump-down? which is produced by a lead ing or lagging phase difference between the input and the vco frequency. during phase acquisition, there are two levels of ?pump-up? and two levels of ?pump down? produced for leading and l agging phase difference between the input and vco frequency. this is to allow for greater precision of vco control. the charge pump produces these signal s by holding the integrated frequency information on the external loop-filter capacitor, c lf .. the instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor. 3.4 frequency acquisition loop ?the phase-frequency detector an external crystal of 14.140 mhz is us ed as a reference to keep the vco centered at the last known data rate. this allows the gs1535 to achieve a fast synchronous lock, especially in cases where a known da ta rate is interrupted. the crystal reference is also used to clock internal timers and counters. to keep the optimal performance of the reclocker over all ope rating conditions, the crystal frequency must be 14.140 mhz, +/-50ppm. the go1535 meets this specification and is available from gennum. the vco is divided by a selected ratio whic h is dependant on the input data rate. the resultant is then compared to the crystal frequency. if the divided vco frequency and the crystal frequency are within 1% of each other, the pll is considered to be locked to the input data rate.
gs1535 data sheet 18557 - 8 february 2005 15 of 22 3.5 phase acquisition loop ? the phase detector the phase detector is a digital quadrature phase detector. it indicates whether the input data is leading or lagging with respect to a clock that is in phase with the vco (i-clk) and a quadrature clock (q-clk). when the phase acquisition loop (pa loop) is locked, the input data transition is aligned to the falling edge of i-clk and the output data is re-timed on the rising edge of i-clk. during high input jitter conditions (>0.25ui), q-clk will sample a different value than i- clk. in this co ndition, two extra phase correction signals will be generat ed which instructs the charge pump to create larger frequency corrections for the vco. figure 3-2: phase detector characteristics. when the pa loop is active, the crystal frequency and the incomming data rate are compared. if the resultant is more that 2%, the pll is considered to be unlocked and the system jumps to the fa loop. 3.6 4:1 input mux the 4:1 input mux allows the connection of four independent streams of video/data. these are differential inputs (ddi[3:0] and ddi[3:0] ). the active channel can be selected via the ddi_sel[1:0] pins. table 3-1 shows the input selected for a given state at ddi_sel[1:0]. i-phase alignment edge data re-timing edge q-phase alignment edge 0.25ui 0.8ui i-clk q-clk input data with jitter re-timed output data table 3-1: bit pattern for input select ddi_sel1:0] selected input 00 ddi0 01 ddi1 10 ddi2 11 ddi3
gs1535 data sheet 18557 - 8 february 2005 16 of 22 the ddi inputs are designed to be dc interfaced with the output of the gs1524 cable equalizer. there are on chip 50 ? termination resistor s which come to a common point at the ddi_vt pins. connect a 10nf capacitor to this pin and connect the other end of the capacitor to ground. this end-terminates the transmission line at the inputs for optimum performance. if only one input pair is used, connect t he unused positive inputs to +3.3v and leave the unused negative inputs floating. this he lps to eliminate crosstalk from potential noise that would couple to the unused input pair. 3.7 automatic and manual data rate selection the gs1535 can be configured to manua lly lock to a specific data rate or automatically search for and lock to the incoming data rate. the auto_man pin selects automatic data rate detection mode (auto mode) when high and manual data rate selection mode (manual mode) when low. in auto mode, the ss[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the pll is lock ed to (or previously locked to). the "search algorithm" cycles through the data rates (see figure 3-3 ) and starts over if that data rate is not found. figure 3-3: data rate search pattern note: when the device is in auto mode, the sd/ hd output will toggle when the reclocker is not locked, (ld= low). the logic level of sd/ hd will depend on the current state of the search algorithm. if the device is also in bypass mode, and the sd/ hd signal is used to set the slew rate of the gs1528 cable driver, that slew rate will change dynamically when the reclocker is not locked. in manual mode, the ss[2:0] pins beco me inputs and the data rate can be programmed. in this mode, the search algorithm is disabled and the gs1535's pll will only lock to this data rate. table 3-2 shows the bit pattern at ss[2:0] for the data rate selected (in manual mode) or the data rate that the pll has locked to (in auto mode). 143 mb\s 177 mb\s 270mb\s 360 mb\s 540 mb\s 1.485mb\s power-up
gs1535 data sheet 18557 - 8 february 2005 17 of 22 3.8 bypass mode in bypass mode, the gs1535 passes the data at the inputs, directly to the outputs. there are two pins that control the bypass function: bypass and autobypass. the bypass pin is an active high signal which forces the gs 1535 into bypass mode for as long as a high is asserted at this pin. the autobypass pin is an ac tive high signal which pl aces the gs 1535 into bypass mode only when the pll has not lo cked to a data rate . note that if bypass is high, this will overwrit e the autobypass functionallity. when the gs1535?s pll is not lock ed and bypass = low and autobypass = low, the serial digital output ddo/ddo will produce invalid data. 3.9 dvb/asi operation the gs1535 is designed to re-clock dvb/asi at 270 mb/s. there is a harmonic present in idle patterns (k28.5) which is very close the 177 mb/s data rate (eic 1179). the asi/177 pin, when high will disable th e 177 mb/s search in auto mode. in this mode, the gs 1535 will not lock to 177 mb/s. 3.10 lock the lock detect signal, ld, is an active high output which indicates when the pll is locked. the lock logic with the gs1535 includes a system which monitors the frequency acquisition loop and the phase acquisition loop as well as a monitor to detect harmonic lock. table 3-2: data rate indication/selection bit pattern ss[2:0] data rate (mb/s) 000 143 001 177 010 270 011 360 100 540 101 1485/1483.5
gs1535 data sheet 18557 - 8 february 2005 18 of 22 3.11 output drivers the gs1535?s serial digital data outputs (ddo/ddo ) have a nominal voltage of 800mv single ended or 1600mv differential when terminated into 50 ?. the ddo_vtt pin is the common point of two 50 ? termination resistors from the ddo and ddo . this pin can be left open if th e termination exists on the receiving device. 3.12 output mute the ddo_mute pin is provided to allow muting of the retimed output. when the gs1535?s pll is locked and the device is reclocking, setting ddo_mute = low will force the serial digital outputs ddo/ddo to mute. however, if the gs1535 is in by pass mode, (autobypass = high and/or bypass = high), ddo_mute will have no effect on the output.
gs1535 data sheet 18557 - 8 february 2005 19 of 22 4. application reference design 4.1 typical application circuit figure 4-1: typical ap plication circuit asi_177 ddi_sel1 sdo_mute ddi_sel0 ld sd/hd 3.3v 3.3v 3.3v 3.3v 10n 10n 10n 10n 47n gs1535 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ddi0 ddi0_vt ddi0 gnd ddi1 ddi1_vt ddi1 gnd ddi2 ddi2_vt ddi2 gnd ddi3 ddi3_vt ddi3 gnd ddi_sel0 ddi_sel1 bypass autobypass auto/man vcc_vco vee_vc0 ss0 ss1 ss2 asi/177 ld rsvd vcc_dig vee_dig gnd sd/hd kbb gnd ddo_mute gnd rsvd rsvd rsvd vcc_int vee_int gnd ddo ddo_vtt ddo vcc_ddo vee_ddo gnd xtal_out+ xtal_out- xtal+ xtal- gnd vcc rsvd vcc rsvd rsvd vee_cp vcc_cp lf+ lf- gnd 10n 65 10n (14.140mhz) 10n 10n 10n data input 1 data input 0 data input 3 data input 2 data output zo = 50 zo = 50 zo = 50 zo = 50 zo = 50 3.3v 3.3v 10n 56 go1535 note: all resistors in ohms and all capacitors in farads.
gs1535 data sheet 18557 - 8 february 2005 20 of 22 5. references compliant with smpte 292m, smpte 259m and smpte344m. 6. package & ordering information 6.1 package dimensions 0 0 0 0 t ab le x t olerances of form and position symbol min nom max min nom max millimeter inch 64l b e aaa ccc b b b d2 e2 0.17 0.50 bsc 0.020 bsc 7.50 0.20 0.20 0.08 0.008 0.008 0.003 0.295 0.295 7.50 0.20 0.27 0.007 0.008 0.011 no te: diag r am sho wn is representativ e only . t ab le x is fix ed f or all pin siz es , and t ab le y is specific to the 64-pin pac kage . t ab le y
gs1535 data sheet 18557 - 8 february 2005 21 of 22 6.2 packaging data 6.3 ordering information parameter value package type 10mm x 10mm 64-pin lqfp package drawing reference jedec ms026 moisture saturation level 3 junction to case thermal resistance, j-c 14.9c/w junction to air thermal resistance, j-a (at zero airflow) 45.4c/w psi 0.9c/w pb-free and green yes part number package temperature range pb-free and green GS1535-CFU 64 pin lqfp 0c to 70c no GS1535-CFUe3 64 pin lqfp 0c to 70c yes
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2002 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs1535 data sheet 18557 - 8 february 2005 22 22 of 22 document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time wit hout notice to improve reliability, function or design, in order to provide the best product possible. 7. revision history version ecr date changes and / or modifications 7 134667 november 2004 corrected tac pinout for pins 50, 51. added packaging data section. updated pins 62 and 63 on the typical application circuit. converted to new document template. 8 135363 january 2005 corrected block diagram and pin description table to reflect mute functionality of the device.

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